Arithmetic Pipeline

Arithmetic Pipeline

• A digital computer performs fixed–point or integer arithmetic and floating point arithmetic. In modern computers, these two functions (integer arithmetic and floating point arithmetic) are performed by two separate units to introduce parallelism. These arithmetic units perform scalar operations involving one pair of operands at a time.

• Let us consider a floating point adder / subtractor with two normalized floating–point binary inputs A and B.

A = m_A × 2^e A

B = m_B × 2 ^e B

where

m_A and m_B are the two fractions those represent the mantissas

e_A and e_B are the two exponents.

• We know that, to perform floating point addition / subtraction we have to perform following suboperations.

■ Exponent comparison

■ Equalize or align the mantissas and choose larger exponent.

■ Add / subtract Mantissas

■ Normalize the result

• These four sub operations are divided into four different stages. In the first stage exponent comparison is carried out by subtracting them. In the second stage the w larger exponent is chosen as the exponent of the result.

The result of the comparison, i.e. difference in the first stage determines how many times the mantissa associated with the smaller exponent must be shifted right to align the mantissas. This subtask is also performed in second stage. In the third stage, two mantissas are added or subtracted. Finally, the result is normalized in the stage four. If an overflow occurs, the mantissa of the result is shifted right and the exponent is incremented by one. If an underflow occurs, the mantissa is shifted left and exponent is decremented by a number equal to the number of leading zeros in the mantissa. The flow chart in Fig. 9.2.1 illustrates above discussed pipelined stages. Registers shown in the flowchart stores the result of the suboperations.

Example: 1

Let us consider that we have to add number A and number B.

where  

A =  m_A x 2 ^e A = 0.10110 × 2³ and

B = m_B x 2 ^e B = 0.11010 × 2⁴

Now we see how suboperations are performed in different stages.

Solution :

Stage 1 : Exponent comparison

| е_A – е_B | = | 3 – 4 | = 1

Stage 2 : Align the mantissas and choose larger exponent

1. Exponent of the result is = e_B = 4.

2. Mantissa m_A = 0.01011

                    A  = 0.01011 × 2⁴ and

                    B = 0.11010 × 2⁴

Stage 3 : Add mantissas

Mantissa of result m_R = 0.01011 + 0.11010 = 1.00101

                                R = 1.10101 × 2⁴

Stage 4 : Normalize the result

R = 0.100101 × 2⁵

Mantissa is shifted right by one digit so that it has a fraction with a nonzero first digit, and exponent is incremented by one.

We know that, the comparator, shifter, incrementer, decrementer and add / subtractor used in implementation of floating point addition / subtraction pipeline are the combinational circuits. They introduce time delays to produce output. Suppose that due to these delays we have time delays in the four stages of pipeline. These are : t₁ = 50 ns, t₂ = 80 ns, t₃ = 90 ns and t₄ = 80 ns. In addition to this there is an interstage delay d = 10 ns. The time period for clock cycle is given by

t =  = 90 ns + 10 ns = 100 ns

The amount of time required to perform floating point addition / subtraction using a non–pipeline floating point adder / subtractor will be

T₁ = t₁ + t₂ + t₃ + t₄ + d = 50 + 80 + 90 + 80 + 10 = 310 ns

Therefore, the speed up factor for this particular pipeline is

S₄ = 310 ns / 100 ns = 3.1

Example: 2

The time delay of the four segment (fetch instruction, decode and calculate effective address, fetch operand, and execute instruction segment) are as follows :

t₁ = 40 ns, t₂ = 25 ns, t₃ = 85 ns, t₄ = 55 ns

The interface registers delay time t_r = 5 ns

i) How long would it take to add 75 pairs of numbers in the pipeline?

ii) How can we reduce the total time to about one half of the time calculated in part (i)?

Solution:

i) Minimum clock cycle for pipeline

= Maximum delay through a stage + Delay time for interface register

= 85 + 5 = 90 ns

Number of cycles required to add 75 pairs of numbers

= k + n − 1 = 4 + 75 – 1 = 78

Time required to execute 75 pairs of numbers

= 78 × 90 = 7020 ns

ii) One–half time of part (i) = 7020 / 2 = 3510 ns

Minimum clock cycle of pipeline = 3510 / 78 = 45 ns

Maximum delay through stage = 45 – 5 = 40 ns

Thus keeping maximum delay through stage equal to 40 ns we can reduce the total time to 3510 ns.

Example: 3

How would you use the floating point pipeline address to add 50 floating point nt pipeline address  numbers.

Solution :

In this section we have seen the pipeline for floating–point addition. By using the same pipeline we can add 50 floating point numbers. In each clock cycle stage 1 gets two fractions and two mantissas of two numbers. As explained earlier, the entire floating point addition operation is carried out in 4 stages. Thus to add 50 floating point numbers total 4 + (50 − 1) = 53 cycles are required.

Review Question

1. What is arithmetic pipeline? Explain arithmetic pipeline for floating point adder/subtractor with the help of one example.