Advanced ILP and Parallel Processing: Two Marks Important Questions and Answers

Computer Organization and Architecture

Chapter 5: Advanced ILP and Parallel Processing

 

Two Marks Questions with Answers

 

1. Define parallel processing.

To fulfil increasing demands for higher performance it is necessary to process data concurrently to achieve better throughput instead of processing each instruction sequentially as in a conventional computer. Processing data concurrently is known as parallel processing.

2. Define multiprocessors.

System may have two or more processors operating concurrently.

We know that, the earlier processors had only one Arithmetic and Logic Unit (ALU) in its CPU. Furthermore, the ALU could only perform one function at a time, resulting quite slow Processing process for executing a long sequence of arithmetic and logical instructions.

3. Define multiprocessor system.

Answer: A computer system with at least two processors is called multiprocessor system.

4. Define task‒level or process level parallelism.

Answer: Utilizing multiple processors for executing independent programs simultaneously is known as task‒level parallelism or process‒level parallelism.

5. Define parallel processing program.

Answer: It is referred to a single program that runs on multiple processors simultaneously.

6. What is cluster ?

Answer: A set of computers connected over a local area network that function as a single large multiprocessor is called cluster.

7. What is multicore ?

Answer: A multicore is an architecture design that places multiple processors on a single die (computer chip) to enhance performance and allow simultaneous processing of multiple tasks more efficiently.

8. What do you mean by CMPs ?

Answer: The multicore architecture designs that allow single chip multiprocessing are known as Chip Multiprocessors (CMPs).

9. What are the limitations to increase clock frequency or processor speed?

Answer:

■ Higher frequency requires more power.

■ More power consumption results it harder and more expensive to cool the system.

■ More power consumption also affects sizing and packaging considerations.

10. Define SMPS.

One of the important aspect of multicore architecture is that, there is no real significant difference between programming for multiple processors in separate packages and programming for multiple processors contained in a single package on a single chip. Thus software developers who are familiar with multiprocessing can easily switch to multicore development.

These multicores are almost always Shared Memory Processors (SMPs), as they usually share a single physical address space.

11. State the need for speculation.

Answer: It is the most important methods for finding and exploiting more ILP.

12. What is ILP? Why is it needed?

Answer:

When instructions in a sequence are independent and can be executed in parallel by overlapping, there is an Instruction Level Parallelism (ILP). Since instructions are executed in parallel it is very much needed to achieve high performance.

13. What is issue slots ?

Answer: The positions from which instructions could issue in a given clock cycle is called issue slot.

14. What is issue packet ?

Answer: It is the set of instructions that issues together in one clock cycle is called issue packet. The packet may be determined statically by the compiler or dynamically by the processor.

15. What is speculation?

Answer: An approach that allows the compiler or the processor to "guess" the outcome of an instruction to remove it as a dependence in executing other instructions is called speculation.

16. What is VLIW ?

Answer: VLIW stands for Very Long Instruction Word (VLIW). It is a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields.

17. Define use latency.

Answer: Number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline is called use latency.

18. Define register renaming.

Answer: During the unrolling process, the compiler introduces additional registers to eliminate dependences that are not true data dependences, but could either lead to potential hazards. The goal of this process, is called register renaming.

19. Define anti‒dependence or name dependence.

Answer: An ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions is called anti‒dependence or name dependence.

20. Define superscalar.

Answer: It is an advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution.

21. Define super scalar processor.

Answer: A processor capable of parallel instruction execution and having performance level greater than one instruction per cycle is known as superscaler processor.

22. What is multiple issue?

Answer: A scheme whereby multiple instructions are launched in one clock cycle is called multiple issue.

23. What is static multiple issue?

Answer: An approach for implementing a multiple‒issue processor where many decisions are made by the compiler before execution is called static multiple issue.

24. What is dynamic multiple issue?

Answer: An approach for implementing a multiple‒issue processor where many decisions are made during execution by the processor is called dynamic multiple issue.

25. What is dynamic pipeline scheduling ?

Answer: Dynamic pipeline scheduling is a hardware support for reordering the order of instruction execution so as to avoid stalls.

26. Define commit unit.

Answer: It is the unit in a dynamic or out‒of‒ order execution pipeline that decides when it is safe to release the result of an operation to programmer‒ visible registers and memory.

27. Define reservation station.

Answer: It is a buffer within a functional unit that holds the operands and the operation.

28. Define reorder buffer.

Answer: The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register is called reorder buffer.

29. What is out‒of‒order execution ?

Answer: A situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait is called out‒of‒order execution.

30. What is in‒order commit ?

Answer: A commit in which the results of pipelined execution are written to the programmer‒visible state in the same order that instructions are fetched is called in‒order commit.

31 State the primary methods to increase ILP.

Answer: There are two primary methods for increasing the potential amount of instruction‒level parallelism. The first is increasing the depth of the pipeline to overlap more instructions and second is to replicate the internal components of the computer so that it can launch multiple instructions in every pipeline stage.

32. What is multiple issue?

Answer: A technique by which multiple instructions are launched in one clock cycle is called multiple issue.

33. What is Instruction‒Level Parallelism (ILP) ?

Answer:

Instruction‒Level Parallelism (ILP) is the ability of a processor to execute multiple instructions simultaneously. It is achieved by identifying independent instructions in a program and executing them in parallel to improve performance and reduce execution time.

34. What is the role of a superscalar processor in exploiting ILP ?

Answer: A superscalar processor issues and executes multiple instructions in a single clock cycle. It uses hardware to dynamically select independent instructions and execute them in parallel pipelines. Most modern CPUs (Intel, AMD, ARM) use superscalar designs to increase ILP.

35. What is register renaming and why is it important for ILP?

Answer: Register renaming is a hardware technique where the processor assigns extra physical registers to eliminate false dependencies like WAR and WAW. This prevents pipeline stalls, allows more instructions to run in parallel, and improves ILP. It is typically implemented using rename tables and the Reorder Buffer (ROB).

36. How does speculation improve ILP?

Answer: Speculation allows the CPU to execute instructions ahead of time based on predicted branch outcomes.

• If the prediction is correct, performance improves.

• If wrong, speculative results are discarded using the ROB.

• Speculation works together with branch prediction and enables higher instruction throughput.

37. What is dynamic scheduling in ILP ?

Answer: Dynamic scheduling is a technique where the hardware (not the compiler) decides the order of instruction execution during runtime.

It allows the processor to:

• Avoid stalls caused by data hazards

• Execute independent instructions out of order

• Improve pipeline efficiency and ILP

38. What is the role of the Reorder Buffer (ROB) in ILP?

Answer: The Reorder Buffer (ROB) stores results of out‒of‒order executed instructions and commits them in correct program order.

Its functions include:

• Supporting register renaming

• Holding speculative results

• Ensuring precise exceptions

• Allowing safe recovery from branch mispredictions

• ROB is essential for implementing out‒of‒order execution and speculation.

39. What is the purpose of branch prediction in modern processors ?

Answer: Branch prediction is used to guess the outcome of branch instructions before the actual result is known. This prevents pipeline stalls caused by control hazards and allows the processor to continue fetching and executing instructions, thereby increasing Instruction‒Level Parallelism (ILP). Accurate branch prediction reduces wasted cycles and improves performance.

40. What are true data dependencies (RAW), and why do they limit ILP?

Answer: True data dependencies, also called Read After Write (RAW) hazards, occur when an instruction requires the result of a previous instruction. Since the dependent instruction must wait for the earlier one to finish, these dependencies cannot be eliminated by hardware. They fundamentally restrict how many instructions can be executed in parallel, thus limiting ILP.

41. Why can real processors not achieve the ILP of an ideal processor ?

Answer: Real processors have limited hardware resources such as a finite number of ALUs, FPUs, register rename entries, and small instruction windows. Additionally, memory delays, cache misses, and branch mispredictions reduce performance. Designing very wide superscalar processors is costly, complex and consumes high power. Hence, real ILP remains far below theoretical maximums.

42. What modern trends have emerged due to the limited growth of ILP ?

Answer: Because ILP improvements show diminishing returns, modern processors now focus on other forms of parallelism, such as:

Multicore processors : Multiple independent cores on a single chip

Simultaneous Multithreading (SMT): Running instructions from multiple threads on one core

Vector units (SIMD) : Executing operations on multiple data elements in parallel

These techniques provide greater performance gains than relying only on ILP.

43. What is multithreading?

Answer: A mechanism by which the instruction streams is divided into several smaller streams (threads) and can be executed in parallel is called multithreading.

44. What is hardware multithreading?

Answer: Increasing utilization of a processor by switching to another thread when one tread is stalled is called hardware multithreading.

45. What is thread ?

 Answer: In multithreading, the instruction stream is divided into several smaller streams, called threads, such that the threads can be executed in parallel.

A thread includes the program counter, stack pointer and its own area for a stack. It executes sequentially and can be interrupted to transfer control to an another thread.

46. What is process?

Answer: A process is an instance of a program running on a computer.

47. What is process switch?

Answer: A process switch is an operation that switches the process or control from one process to another. It first saves all the process control data, registers and other information and then replaces them with the process information for the second.

48. What is thread switch?

Answer: A thread switch is an operation that switches the processor control from one thread to another within the same process. This is cheaper than a process switch.

49. Give the comparison between process switch and thread switch.

Process switch

1. It is an operation that switches the process or control from one process to another.

2. When the processor control is transferred from one process to another, the control or ownership of resources is also transferred. So process switch is time consuming than thread switch.

3. It is much costly than a thread switch.

Thread switch

1. It is an operation that switches the processor control from one thread to another thread.

2. The multiple threads within a process share the same resources. So a thread switch is much less time consuming than a process switch.

3. It is much less costly than process switch.

50. What are explicit threads ?

Answer: User level threads which are visible to the application program and kernel‒level threads which are visible only to operating system, both are referred to as explicit threads.

51. What do you mean by implicit multithreading?

Answer: Implicit multithreading refers to the concurrent execution of multiple threads extracted from a single sequential program.

52. What do you mean by explicit multithreading?

Answer: Explicit multithreading refers to the concurrent execution of instructions from different explicit threads, either by interleaving instructions from different threads on shared pipelines or by parallel execution on parallel pipelines.

53. Define interleaved or fine‒grained multithreading.

Answer: A version of hardware multithreading that suggests switching between threads after every instruction is called interleaved or fine‒grained multithreading.

54. Define blocked or coarse‒grained multithreading.

Answer:

A version of hardware multithreading that suggests switching between threads only after significant events, such as a cache miss is called blocked or coarse‒grained multithreading.

55. Define simultaneous multithreading (SMT).

Answer: A version of multithreading that lowers the cost of multithreading by utilizing the resources needed for multiple issue (dynamically schedule microarchitecture) is called simultaneous multithreading (SMT).

56. What is chip multiprocessing ?

Answer: The processor is replicated on a single chip and each processor executes separate threads. This approach effectively utilizes the available logic data on a chip without increasing pipeline design complexity. This is referred to as chip multiprocessing.