Multiple-Issue Processor

Multiple‒Issue Processor

• There are two major ways to implement a multiple‒issue processor, according to the division of work between the compiler and the hardware.

■ Static multiple issue : Here, the decisions of division of work are being made statically, i.e., at compile time before execution.

■ Dynamic multiple issue : Here, the decisions of division of work are being made dynamically i.e., at execution time by the processor.

• There are two primary and distinct responsibilities that must be taken care of within a multiple‒issue pipeline:

■ Packaging instructions into issue slots (The positions from which instructions could issue in a given clock cycle.

■ Dealing with data and control hazards.

1. Static Multiple Issue Processors

• Static multiple‒issue processors all use the compiler to assist with packaging instructions and handling hazards.

• A static multiple‒issue processor usually launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. Such a style of instruction set architecture is known as Very Long Instruction Word (VLIW).

2. Dynamic Multiple Issue Processors

• Processors such as the PowerPC reach performance levels greater than one instruction per cycle by fetching, decoding and executing several instructions concurrently. This mode of operation is called superscaler. A processor capable of parallel instruction execution and having performance level greater than one instruction per cycle is known as superscaler processor.

• A superscaler processor has multiple execution units (E‒units), each of which is usually pipelined, so that they constitute a set of independent instruction pipelines. Its Program Control Unit (PCU) is capable of fetching and decoding several instructions concurrently. It can issue upto k instructions simultaneously to the various E‒units. Where k is called instruction issue degree. It can be six or more using current technology.

• To fetch, decode and execute several instruction concurrently, the superscaler operation requires processor to detect and exploit instruction‒level parallelism hidden in the programs it executes. It has to handle following important issues :

■ Instruction type : A floating‒point add instruction has to be issued to a floating point E‒unit and not to an integer E‒unit.

■ E‒unit availability : An instruction can be issued to a pipelined E‒unit only if no collision will result, as determined by the pipeline's reservation table.

■ True data dependency.

■ Procedural dependency.

■ Resource conflicts.

■ Output dependency.

■ Antidependency.

True data dependency

• Let us see the following instructions :

■ Sub r₁, r₂; Subtract the contents of r₂ from r₁ and store the result in r₁.

■ Move r₃, r₁; Load register r₃ with the contents of r₁.

• In the above instruction sequence, the second instruction can be fetched and decoded, but cannot be executed until the first instruction executes. The reason is that the second instruction requires the data produced by the first instruction. This situation is referred to as a true data dependency. This limits the performance of any type of pipeline.

Procedural dependency

• We have seen earlier that the branch instructions complicate the pipeline operation. There are branch prediction techniques, but they cannot improve performance hundred percent. In branch prediction technique, taken or not taken, we cannot execute instruction until branch is executed. This situation is referred to as procedural dependency.

Resource conflict

• While executing number of instructions in parallel, the situation may occur that two or more instructions require same resource at the same time. For example, two or more instructions may require references to memories, caches, buses register‒file ports and functional units at the same time. This situation is referred to as resource conflict.

Output dependency

• Let us see the following instructions :

R3 = R3+ R5 ← Il

R4 = R3+1 ← 12

R3 = R5+1 ← 13

R6 = R3+ R4 ← 14

• In the above instruction sequence I3 cannot execute instruction I2 before I1 because of the true data dependency and for similar reasons we also cannot execute instruction I4 before I3. But there is one more dependency which exists between instruction I3 and instruction I1. We cannot execute instruction I3 before instruction I1, because if 13 executes prior to completion of I1, then wrong value of the contents of R3 will be fetched for the execution of instructions I1 and I4. This situation is referred to as output dependency.

Antidependency

• Let us see the following instructions :

R3 = R3 + R5 ← I1

R4 = R3+1  ← 12

R3 = R5+ 1 ← I3

R6 = R3+ R4 ← 14

• In the above instruction sequence instruction I3 cannot be completed its execution before instruction I2 begins execution and had fetched its operands. This is so because instruction I3 updates register R3, which is a source operand for instruction I2. This situation is referred to as antidependency. Here, constraints are exactly reverse that of true data dependency.

Control dependencies : To maintain high performance levels, techniques are needed to reduce the impact of branch instructions on pipeline efficiency.

Program order:

• Instructions must eventually produce results in the order specified by the program being executed. The result may, however, be computed out‒of‒order internally to improve the CPU's performance.

Review Questions

1. What is static multiple issue and dynamic multiple issue?

2.What is VLIW?