Computer Organization and Architecture

CW25201:

Computer Organization and Architecture

Course Objectives

• To introduce the fundamental components of digital computer systems.

• To explain various Instruction Set Architecture (ISA) types and instruction execution processes.

• To impart knowledge on system performance metrics and evaluation techniques.

Introduction: Functional Units of a Digital Computer, Classes of Computer Systems, Hardware-Software Interface, Operation and Operands of Computer Hardware, Instruction Set Architecture, RISC and CISC Architectures, Addressing Modes, Assembly Language Programming, Translation from High-Level Language to Machine Language, Performance Metrics, Benchmarks, Transition from Uniprocessors to Multiprocessors

Activities:

• C code to machine code mapping.

• Assembly of computer system components

Arithmetic for Computers: Integer Arithmetic, Binary Parallel Adder, Carry Lookahead Adder, Carry Save Adder, Fast Adders, Binary Multiplication, Booth’s Algorithm, Bit Pair Recoding, Binary Division, Restoring and Non-Restoring Division, Floating Point Numbers (Single and Double Precision), Floating Point Representation, Arithmetic Operations on Floating Point Numbers, ALU Design, Parallelism and Computer Arithmetic.

Activities:

• Arithmetic Operations

• Restoring / non-restoring division

Processor Design: Design Conventions of a Processor, Datapath Design, Building the Datapath, Implementation of Basic MIPS ISA, Designing the Control Unit, Simple Implementation Scheme and Drawbacks, Execution of a Complete Instruction, Hardwired and Microprogrammed Control, Instruction Level Parallelism, Basic Concepts of Pipelining, Pipelined Datapath and Control, Performance, Pipeline Hazards – Structural, Data, and Control Hazards, Handling Exceptions.

Activities:

• CPU datapath analysis.

• Pipeline hazard analysis.

Memory and I/O: Types of Memories, Need for a Hierarchical Memory System, Cache Memories, Memory Mapping, Measuring and Improving Cache Performance, Virtual Memory, Paging and Segmentation, TLB, Implementing Protection with Virtual Memory, Memory Management Techniques, Associative Memories, Introduction to Virtual Machines, Memory and I/O Devices, Interfacing I/O Devices to the Processor, Memory and Operating System, Programmed Input/Output, Interrupts, Direct Memory Access (DMA), RAID.

Activities:

• CPU Cortex memory hierarchy.

• Cache memory mapping

Advanced ILP and Parallel Processing: Advanced Instruction Level Parallelism (ILP), Exploitation of ILP, Out-of-Order Execution, Dynamic Scheduling, Speculation, Dynamic Branch Prediction, Multiple Issue Processors – Static and Dynamic, Limitations of ILP, Multithreading.

Activities:

• Out-of-Order Execution and Dynamic Scheduling

• Virtual Demonstration of processor performance in real workloads

Next Generation Computer Architecture: Multicore Architectures, Superscalar Processors, VLIW, Introduction to Multicore and Multiprocessor Systems, Graphics Processing Units (GPU), CUDA Programming Paradigm, Neural Processing Units (NPU), AI Processing Chips (AI PC), Overview of Next Generation Processors.

Activities

• ILP Pipeline Simulation

• Dynamic branch prediction strategies

Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%

Assessment Methodology: Assignments (10%), Quiz (5%), Project based learning (20%), Flipped Classroom (5%), Review of GATE questions (10%) & Internal Assessment (50%)

References:

1. Stallings, W. (2016). Computer organization and architecture: Designing for performance. Pearson Education.

2. Hennessy, J. L., & Patterson, D. A. (2019). Computer architecture: A quantitative approach. Morgan Kaufmann / Elsevier Publishers.

3. Hayes, J. P. (2017). Computer organization and architecture. Tata McGraw Hill.

4. Sarangi, S. R. (2023). Next-gen computer architecture. White Falcon Publishing.

5. Patterson, D. A., & Hennessy, J. L. (2020). Computer organization and design: The hardware/software interface. Morgan Kaufmann / Elsevier.

6. Heuring, V. P., & Jordan, H. F. (2004). Computer systems design and architecture.

Pearson Education.