Handling Exceptions

Handling Exceptions

• One of the difficult parts of control is to implement exceptions and interrupts‒events other than branches or jumps that change the normal flow of instruction execution.

• Exceptions are internally generated unscheduled events that disrupt program execution and they are used to detect overflow. On the other hand, interrupt comes from outside of the processor.

• Arithmetic overflow, invoking the operating system from user program and using an undefined instruction are internally generated events and hence called exceptions.

• I/O device request is an externally generated event and hence called interrupt.

• Hardware malfunctions may be either externally generated event or internally generated event and called either interrupt or exception.

Handling exceptions in the MIPS architecture

Types of exceptions

• The two types of exceptions can occur in the basic MIPS architecture implementation.

■ Execution of an undefined instruction

■ Arithmetic overflow in the instruction add $1, $2, $1.

Response to an exception

• When an exception occurs the processor saves the address of the offending instruction in the Exception Program Counter (EPC) and then transfers control to the operating system at some specified address.

• The operating system then takes the appropriate action, which may involve providing some service to the user program, taking some predefined action in response to an exception, or stopping the execution of the program and reporting an error.

• After performing whatever action is required because of the exception, the operating system either terminates the program or may continue its execution, using the EPC to determine where to restart the execution of the program.

Methods used to communicate the reason for an exception

• To handle the exception, it is must for the operating system to know the reason for the exception and the instruction that caused it. There are two main methods used to communicate the reason for an exception.

■ Status register method: In this method, the MIPS architecture uses a status register (called the Cause register), which holds a field that indicates the reason for the exception.

■ Vectored interrupts method: In this method, vectored interrupts are used. In a vectored interrupt, the address to which control is transferred is determined by the cause of the exception.

Exceptions in a pipelined implementation

• Like branch instruction, a pipelined implementation treats exceptions as another form of control hazard. In case arithmetic overflow exception in an add instruction, we must flush the instructions that follow the add instruction from the pipeline and begin fetching instructions from the new address.

• Multiple exceptions can occur simultaneously in a single clock cycle. In such cases, exception having highest priority is serviced first.

• In pipelined computers, interrupts and exceptions are further classified as:

■ Imprecise interrupts or imprecise exceptions.

■ Precise interrupts or precise exceptions

 • Imprecise interrupts or imprecise exceptions : Interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception are called imprecise interrupts or imprecise exceptions.

• Precise interrupts or precise exceptions : An interrupt or exception that is always associated with the correct instruction in pipelined computers is called precise interrupt or precise exception.

Review Questions

1. Define exception and interrupt.

2. Explain in detail how exceptions are handled in MIPS architecture?

3. State two methods used to communicate the reasons for exception.

4. Define imprecise and precise exceptions.

5. What is an exception? Give one example for MIPS exception.