Instruction Set Architecture (ISA)

Instruction Set Architecture (ISA)

• The Instruction Set Architecture (ISA), or processor architecture, serves as the interface between software and hardware, defining the set of instructions a CPU can execute, their encoding formats and the behaviour they produce.

• It provides a standardized framework that allows programs written for a specific ISA to run on different CPUs implementing the same architecture, ensuring compatibility and portability.

• ISAS guide both software development ‒ by specifying instruction types, addressing modes and registers ‒ and hardware design, by defining registers, memory models, control units and execution pipelines.

• Fig. 1.6.1 shows the relation between ISA, hardware and software.

■ Software uses the ISA to write and execute programs.

■ ISA acts as the bridge, defining instructions, registers, data types, addressing modes, and control mechanisms.

■ Hardware implements the ISA in physical components like CPU, memory and I/O devices, enabling program execution.

Key components of ISA :

1. Instruction set: Includes arithmetic (add, subtract, multiply, divide), logical (AND, OR, XOR), data transfer (load, store), control flow (branch, jump) and specialized instructions (multimedia, cryptography, AI acceleration).

2. Instruction format: Specifies opcode, operand fields, immediate values and control bits, influencing instruction length, encoding efficiency and fetch / decode complexity.

3. Data types: Defines the supported data types, including integers, floating‒point numbers and characters, along with their size and memory representation.

4. Registers: High‒speed storage within the CPU, used for quick data access and intermediate computations. ISA defines the number, size and purpose of registers.

5. Memory model and addressing modes: Specifies how instructions access memory, including direct, indirect, immediate and indexed modes. Endianness (big‒endian Vs little‒endian) is also defined.

6. Input/Output mechanisms: Instructions or dedicated I/O processors enable the CPU to interact with external devices.

7. Interrupts and exceptions: Provide mechanisms for handling asynchronous events (interrupts) and synchronous errors (exceptions).

8. Privilege levels: Support multiple operating modes (user, kernel) to enforce security and system protection.

9. Parallelism support: Some ISAs include vector, SIMD or multithreading instructions to enable high‒performance computing.

10. Microarchitecture independence: The same ISA can be implemented with different pipelines, cache structures4 and execution units, allowing hardware innovation without affecting software.

Importance of ISA :

■ Compatibility and portability: Programs run across different CPUs with the same ISA.

■ Software development: Provides a clear instruction framework, enabling efficient coding, compilation, and optimization.

■ Hardware design: Informs CPU design, including control units, memory access and execution pipelines.

■ Performance optimization: Instruction selection, encoding and parallelism influence speed and efficiency.

■ Security and reliability: Privilege levels, memory protection and exception handling ensure safe operation.

■ Specialization: Different ISAs can be optimized for specific tasks, such as graphics, scientific computing, or AI.

MIPS Architecture

• MIPS is an implementation of a RISC architecture.

• MIPS instruction set architecture has a small set of instructions and addressing modes. It is designed for use with high‒level programming languages.

• MIPS instruction set architecture allows for parallel execution. It minimizes the amount of work (computation and data flow) per instruction.

• MIPS instruction set architecture provides a large register set, minimizing main memory access.

• MIPS instruction set architecture has fixed instruction width (32‒bits) and a small set of uniform instruction encodings, which minimizes control complexity and allows for more registers.

• MIPS instructions can be categorized as :

 ■ Arithmetic/logical / shift/comparison

 ■ Control instructions (branch and jump)

 ■ Load/store

 ■ Other (exception, register movement to/from GP registers, etc.)

• MIPS instruction set architecture has three instruction encoding formats: R‒type, I‒type and J‒type.

Review Questions

1. Write a note on Instruction Set Architecture (ISA).

2. What is the importance of ISA?

3. List the features of MIPS instruction set architectu