Superscalar Processors

Superscalar Processors

• A superscalar processor is a type of Central Processing Unit (CPU) that implements a form of parallelism known as Instruction‒Level Parallelism (ILP) within a single processor. Unlike earlier processors that could execute at most one instruction per clock cycle, a superscalar design enables the CPU to execute multiple instructions simultaneously in a given clock cycle by utilizing multiple execution units.

1. Superscalar Architecture and Operation

• A superscalar processor is characterized by the following architectural elements:

1. Multiple Execution Units (E‒units) : The processor contains several independent functional units, such as Integer ALUS, Floating‒Point Units (FPUs) and Load/Store Units (LSUs). These units are typically pipelined themselves, forming a set of parallel instruction pipelines.

2. Program Control Unit (PCU) : The PCU is enhanced to fetch and decode several instructions simultaneously.

3. Instruction Issue Logic : This complex unit, often called the instruction scheduler, is responsible for determining which decoded instructions can be safely dispatched to the available E‒units for parallel execution. The issue logic is critical as it must determine if instructions are independent (i.e., whether the execution of one instruction is dependent on the result of another). The number of instructions that can be issued simultaneously is known as the instruction issue degree (k).

• To successfully exploit ILP and achieve high performance, the processor must detect and manage various dependencies and conflicts inherent in the instruction stream.

2. Challenges in Superscalar Execution

• To fetch, decode and execute several instruction concurrently, the superscaler operation requires processor to detect and exploit instruction‒level parallelism hidden in the programs it executes. It has to handle following important issues:

■ Instruction type : A floating‒point add instruction has to be issued to a floating point E‒unit and not to an integer E‒unit.

■ E‒unit availability : An instruction can be issued to a pipelined E‒unit only if no collision will result, as determined by the pipeline's reservation table.

■ True data dependency

■ Procedural dependency

■ Resource conflicts

■ Output dependency

■ Antidependency.

True data dependency

■ Let us see the following instructions:

 ♦ Sub г₁, r₂ ; Subtract the contents of r₂ from r₁ and store the result in r₁

 ♦ Move г₃,г₁; Load register r₃ with the contents of r₁

 ♦ In the above instruction sequence, the second instruction can be fetched and decoded, but cannot be executed until the first instruction executes. The reason is that this the second instruction requires the data produced by the first instruction. This situation is referred to as a true data dependency. This limits the performance of any type of pipeline.

Procedural dependency

■ We have seen earlier that the branch instructions complicate the pipeline operation. There are branch prediction techniques, but they cannot improve performance hundred percent. In branch prediction technique, taken or not taken, we cannot execute instruction until branch is executed. This situation is referred to as procedural dependency.

Resource conflict

■ While executing number of instructions in parallel, the situation may occur that two or more instructions require same resource at the same time. For example, two or more instructions may require references to memories, caches, buses register‒file ports and functional units at the same time. This situation is referred to as resource conflict.

Output dependency

■ Let us see the following instructions.

R3 = R3 + R5 ← I1

R4 = R3 +1 ← 12

R3 = R5+1  ← 13

R6 = R3 + R4 ← 14

■ In the above instruction sequence we cannot execute instruction I2 before I1because of the true data dependency and for similar reasons we also cannot execute instruction I4 before I3. But there is one more dependency which exists between instruction I3 and instruction I1. We cannot execute instruction I3 before instruction I1, because if I3 executes prior to completion of I1, then wrong value of the contents of R3 will be fetched for the execution of instructions I1 and I4. This situation is referred to as output dependency.

Antidependency

• Let us see the following instructions

R3 = R3+ R5 ← I1

R4 = R3+1 ← 12

R3 = R5+ 1 ← 13

R6 = R3+ R4 ← 14

• In the above instruction sequence instruction I3 cannot be completed its execution before instruction I2 begins execution and had fetched its operands. This is so because instruction I3 updates register R3, which is a source operand for instruction I2. This situation is referred to as antidependency. Here, constraints are exactly reverse that of true data dependency.

Control dependencies : To maintain high performance levels, techniques are needed to reduce the impact of branch instructions on pipeline efficiency.

Program order :

• Instructions must eventually produce results in the order specified by the program being executed. The result may, however, be computed out‒of‒order internally to improve the CPU's performance.

3. Instruction‒Issue Policy

■ Considering the limitations of parallelism processor must able to identify the next instruction to be fetched, decoded and executed. This process is known as instruction issue and each processor has its own instruction issue policy.

• Superscalar processors use following instruction issue policies.

■ In‒order issue with in‒order completion

■ In‒order issue with out‒of‒order completion

■ Out‒of‒order issue with out‒of‒order completion.

In‒order Issue with In‒order Completion

■ In this policy instructions are executed in exact order that would be achieved by sequential execution.

■ Let us consider the instructions with following constraints :

♦ I1 requires two cycles to execute

♦ I3 and I4 conflict for function unit

♦ I5 depends on the value produced by I4

♦ I5 and I6 conflict for function unit.

■ With above constraints in‒order issue with in‒order completion policy executes all instructions as shown in Fig. 6.2.1.

In‒order Issue with Out‒of‒order Completion

■ If any instruction requires multiple cycles and the next instruction is independent of current instruction then it is allowed to execute before the completion of current instruction. This policy is referred to as in‒order issue with out‒of‒order completion. This policy is used in scalar RISC processors to improve the performance of the instructions that require multiple cycles. Fig. 6.2.2 shows the modified execution sequence due to this policy. As shown in Fig. 6.2.2 the net result is saving of one cycle.

Out‒of‒order Issue with Out‒of‒order Completion

■ With in‒order issue, the processor decodes the instructions upto the point of a dependency or conflict. But in out‒of‒order issue, processor decodes the instruction beyond any dependency or conflict, to achieve look ahead capacity, allowing it to identify independent instructions that can be brought into the execute stage. To implement this, processor provides buffer commonly known as instruction window where decoded instructions are stored. Fig. 6.2.3 shows the modified execution sequence due to this policy.

4. Register Renaming

• Register renaming is a hardware technique used in modern superscalar and out‒of‒order processors to eliminate false data dependencies that occur due to the reuse of a limited number of architectural registers. By doing so, it exposes more Instruction‒Level Parallelism (ILP) and allows the CPU to execute instructions more efficiently and out‒of‒ order.

• Modern CPUs have a small, fixed number of architectural registers defined by the instruction set (e.g., R1, R2, F0). When a program is compiled, these registers are reused across multiple instructions. This reuse can create false dependencies (Anti‒dependency, Output dependency) that unnecessarily stall instruction execution.

• Register renaming takes the small set of registers that a programmer can see (like R1, R2, etc.) and maps them to a larger set of hidden physical registers inside the CPU.

1. When the CPU decodes an instruction, it gives a new, unused physical register for the instruction's output.

2. The CPU keeps a Map Table (also called Register Alias Table) to remember which physical register currently holds the latest value of each visible register.

• This prevents two instructions from accidentally using the same register at the same time.

• It removes artificial delays caused by "fake" dependencies, allowing the CPU to execute instructions faster and out‒of‒order.

Review Questions

1. What do you mean by superscalar processor?

2. List the issues which must be considered in implementation of superscaler processor.

3. Discuss various instruction issue policies.

4. What is register renaming?