RISC Vs CISC Architecture

RISC Vs CISC

• Instruction Set Architectures can be broadly categorized into two types : Complex Instruction Set Architecture (CISC) and Reduced Instruction Set Architecture CHTE (RISC).

1. Complex Instruction Set Architecture (CISC)

2. Reduced Instruction Set Architecture CHTE (RISC)

1. CISC Architecture

• CISC is an acronym for Complex Instruction Set computers or computing. It is based on the concept of using very large instruction set having simple as well as complex instructions and making instruction set more flexible to keep program length as small as possible.

• In CISC complex instructions may take multiple cycles for execution.

• CISC instructions vary in size, often specify a sequence of operations, and can require serial (slow) decoding algorithms.

• They tend to have few registers, and the registers may be special purpose, which restrict the way in which they can be used.

• In CISC, there are many instructions that support memory reference. For example, we can add memory contents to the registers.

• CISC instruction sets are designed to take advantage of microcode.

• To add the flexibility in the instruction set, they support more and complex addressing modes.

• Example of CISCs are : Intel X86, Motorola 68000 series, DEC VAX, etc.

2. RISC Architecture

• RISC refers to Reduced Instruction Set Computers or Computing. RISC microprocessors are very different from CISC microprocessors. RISC use concept of keeping the instruction set as simple as possible to allow the microprocessor's program to be written using only simple instructions.

• The designer designed RISC architecture considering following points :

1. A limited and simple instruction set.

2. A large number of general purpose registers, or the use of compiler technology to optimize register usage.

3. An emphasis on optimizing the instruction pipeline.

RISC : Instruction execution and characteristics

• In RISC processors, there is an one instruction per machine cycle.

• RISC machine instructions are not complicated and can execute about as fast as, microinstruction on CISC machines.

• The machine instructions are hardwired. These instructions are executed faster than the instructions implemented with microinstructions.

• This architecture encourages the optimization of register use, so that frequently accessed operands remain in high–speed storage to implement register to register operations. For this RISC processors provide multiple sets of registers.

• RISC processor provides limited number of instructions, which simplifies the design of control unit.

• RISC processor uses simple addressing modes. Almost all instructions use simple register addressing.

• RISC processors use simple instruction formats with fixed instruction length. The instruction length is aligned on word boundaries. Field locations, especially opcodes are fixed.

Because of this, they provide following benefits :

• With fixed fields, opcode decoding and register operands addressing can occur simultaneously.

• It simplifies the design of control unit.

• Instruction fetching is optimized since word–length units are fetched.

To speed–up instruction execution, RISC uses instruction pipelining.

• Examples of RISCs are : ARM, ATMEL, 8051 family, AVR, MIPS, PIC etc.

3. CISC VS RISC Processor Architectures

Review Questions

1. Define the acronyms CISC and RISC.

2. What is the primary concept or goal each architecture is based on?

3. Compare and contrast CISC and RISC architectures.