Parallel Processing: Two Marks Important Questions and Answers

Digital Principles and Computer Organization:

Chapter 10: Parallel Processing

Two Marks Questions with Answers

 

1. What is Instruction–Level Parallelism (ILP)?

 Answer: Instruction–Level Parallelism (ILP) is a technique that allows multiple independent instructions from a single program to be executed simultaneously to improve processor performance. It increases instruction throughput by overlapping or parallelizing instruction execution.

2. What is the main goal of ILP ?

 Answer: The main goal of ILP is to improve the speed and efficiency of program execution by identifying and executing independent instructions in parallel rather than sequentially.

3. State any two benefits of ILP.

 Answer:

1. Increases instruction throughput – more instructions are completed per unit time.

2. Reduces overall program execution time by overlapping instruction execution.

4. What are the challenges in implementing ILP ?

 Answer:

• Instruction dependencies : Some instructions depend on results of previous ones.

• Resource limitations : Limited number of functional units to execute instructions.

• Control complexity : Managing dependencies and execution order increases hardware complexity.

5. List and briefly explain two techniques used to achieve ILP.

 Answer:

1. Pipelining : Divides instruction execution into stages so multiple instructions can be processed simultaneously in different stages.

2. Out–of–order execution : Allows instructions to execute as soon as their operands are ready, regardless of original program order.

6. What is the difference between pipelining and superscalar execution ?

 Answer:

• Pipelining overlaps stages of multiple instructions within a single pipeline.

• Superscalar execution uses multiple pipelines or execution units to execute multiple instructions in the same clock cycle.

7. What is data forwarding in ILP ?

 Answer: Data forwarding (also called bypassing) is a technique that allows the result of one instruction to be used directly by the next instruction without waiting for it to be written back to a register, reducing execution delays.

8. Define parallel processing.

Answer:

To fulfil increasing demands for higher performance it is necessary to process data concurrently to achieve better throughput instead of processing each instruction sequentially as in a conventional computer. Processing data concurrently is known as parallel processing. There are two basic ways by which we can achieve parallelism.

9. Define multiprocessors.

Answer:

Multiple processors : System may have two or more processors operating concurrently.

Multiprocessor system : A computer system with at least two processors is called multiprocessor system. quio olgnia wolls.

10. Define multiprocessor system.

 Answer:

A computer system with at least two processors is called multiprocessor system.

11. Define task–level or process level parallelism.

 Answer: Utilizing multiple processors for executing independent programs simultaneously is known as Task–level parallelism or process–level parallelism.

12. Define parallel processing program.

 Answer: It is referred to a single program that runs on multiple processors simultaneously.

13. What is cluster ?

 Answer: A set of computers connected over a local area network that function as a single large multiprocessor is called cluster.

14. What is multicore ?

 Answer: A multicore is an architecture design that places multiple processors on a single die (computer chip) to enhance performance and allow simultaneous processing of multiple tasks more efficiently.

15.  What do you mean by CMPs ?

 Answer: The multicore architecture designs that allow single chip multiprocessing are known as Chip Multiprocessors (CMPs).

16. What are the limitations to increase clock frequency or processor speed?

 Answer:

■ Higher frequency requires more power.

■ More power consumption results it harder and more expensive to cool the system

■ More power consumption also affects sizing and packaging considerations.

17. Define SMPS.

One of the important aspect of multicore architecture is that, there is no real lange significant difference between programming for multiple processors in separate packages and programming for multiple processors contained in a single package on a single chip. Thus software developers who are familiar with multiprocessing can easily switch to multicore development.

These multicores are almost always Shared Memory Processors (SMPs), as they usually share a single physical address space.

18. State the Amdahl's law?

 Answer: It states that the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used.

19. What is the use of Amdahl's law ?

 Answer: It tells us how much faster a task can be executed using the machine with the enhancement as compare to the original machine.

20. Define strong scaling.

 Answer: Speedup achieved on a multiprocessor without increasing the size of the problem is called strong scaling.

21. Define weak scaling.

 Answer: Speedup achieved on a multiprocessor while increasing the size of the problem proportionally to the increase in the number of processors is called weak scaling.

22. List four major groups of computers defined by Micheal J. Flynn.

OR

What is Flynn's classification.

 Answer:

• Single Instruction Stream–Single Data stream (SISD).

• Single Instruction Stream–Multiple Data streams (SIMD).

• Multiple Instruction Streams–Single Data stream (MISD).

• Multiple Instruction Streams–Multiple Data streams (MIMD).

23. What is SISD ?

 Answer: SISD stands for Single Instruction stream, Single Data stream, a uniprocessor.

24. What is MIMD ?

 Answer: MIMD stands for Multiple Instruction streams, Multiple Data streams, a multiprocessor.

25. What is SIMD ?

 Answer: SIMD stands for Single Instruction stream, Multiple Data streams, multiprocessor. The same instruction is applied to many data streams, as in a vector processor or array processor.

26. What is data–level parallelism ?

 Answer: Parallelism achieved by performing the same operation on independent data is known as data–level parallelism.

27. Give example for each class in Flynn's classification.

The classification made by Micheal J. Flynn divides computers into four major groups.

■ Single Instruction Stream–Single Data stream (SISD).

■ Single Instruction Stream–Multiple Data streams (SIMD).

■ Multiple Instruction Streams–Single Data stream (MISD).

■ Multiple Instruction Streams–Multiple Data streams (MIMD).

28. What is a superscalar processor ?

 Answer: A superscalar processor is a CPU that can issue and execute multiple instructions per clock cycle by using several parallel execution units. It exploits Instruction–Level Parallelism (ILP) and has hardware like parallel pipelines, advanced decoding, and instruction issue logic.

29. What is the role of the Program Control Unit (PCU) in a superscalar processor ?

 Answer: The PCU fetches and decodes multiple instructions simultaneously. It works with instruction schedulers to supply parallel pipelines with a continuous stream of instructions.

30. What is the meaning of instruction issue degree (k)?

 Answer: Instruction issue degree (k) refers to the maximum number of instructions a processor can issue in one clock cycle.

Example : If k = 4 → processor can dispatch 4 instructions simultaneously.

31. What are the main types of dependencies that affect superscalar execution ?

 Answer: Superscalar processors must manage :

• Data dependencies (RAW, WAR, WAW)

• Control dependencies (due to branches)

• Resource conflicts (multiple instructions needing the same unit)

32. What is a structural hazard in superscalar execution ?

 Answer: A structural hazard occurs when two or more instructions require the same hardware resource at the same time (e.g., ALU, FPU, LSU).

This prevents parallel execution and may cause stalls.

33. What is data dependency checking, and why is it important?

 Answer: Data dependency checking ensures that instructions issued in parallel are independent.

It prevents hazards like RAW, WAR, and WAW, allowing the CPU to issue only safe instructions that won't produce incorrect results.

34. What is an instruction–issue policy?

 Answer: An instruction–issue policy defines how many instructions and which instructions can be issued per cycle. It determines whether issuing is in–order, out–of–order, or hybrid, affecting overall ILP and CPU performance.

35. What is the difference between in–order and out–of–order issue ?

 Answer:

• In–order issue : Instructions are issued in the exact sequence they are fetched.

• Out–of–order issue : Instructions are issued based on data availability and resource availability, not strictly in program order.

• Out–of–order increases ILP and performance.

36. What is register renaming ?

 Answer: Register renaming is a hardware technique that maps architectural registers to a larger set of physical registers to eliminate false dependencies like WAR and WAW.

37. What problem does register renaming solve ?

 Answer: Register renaming removes false dependencies :

• Anti–dependency (WAR)

• Output dependency (WAW)

This allows more instructions to execute in parallel and enables out–of–order execution.

38. What is a Register Alias Table (RAT)?

 Answer: The Register Alias Table (Map Table) stores the mapping between architectural registers and physical registers, ensuring each instruction uses the correct, latest value.

39. How does register renaming improve ILP?

 Answer: By eliminating false dependencies, register renaming exposes more parallelism. Hence, more instructions can be issued simultaneously, improving throughput.

40. What is the role of physical registers in renaming ?

 Answer: Physical registers act as temporary storage locations for instruction results. Each new instruction is assigned a fresh physical register, avoiding overwriting problems.

41. Why do superscalar CPUs require complex instruction scheduling hardware ?

 Answer: Because they must check :

• Data dependencies

• Structural hazards

• Control hazards

Scheduling ensures only independent instructions execute in parallel, avoiding incorrect program behavior.

42. What is a vector processor ?

 Answer: A vector processor is a CPU designed to perform operations on entire arrays (vectors) of data in a single instruction. It uses vector registers and pipelines to achieve high performance on scientific and mathematical computations.

43. What is vectorization ?

 Answer: Vectorization is the process of converting scalar operations into vector operations so that multiple data elements can be processed simultaneously using vector instructions.

44. What are vector registers ?

 Answer: Vector registers are special high–capacity registers that can store multiple data elements (e.g., 64 or 128 elements). They allow a single instruction to operate on all elements in the register.

45. What is the main advantage of vector processors ?

 Answer: The main advantage is high throughput for repetitive arithmetic operations on large data sets (matrix multiplication, scientific simulations, graphics). They reduce loop overhead and improve parallelism.

46. What do you mean by vector pipeline ?

 Answer: A vector pipeline allows each stage of the pipeline to operate on different elements of a vector simultaneously, achieving high speed by overlapping operations on consecutive elements.

47. What is a vector instruction?

 Answer: A vector instruction performs the same operation on multiple data elements at once. Example :

ADDV V1, V2 → V3 adds all elements of V1 and V2.

48. What are the limitations of vector processors ?

 Answer:

• Not suitable for irregular data or operations that depend on previous results

• Requires programmer/compiler vectorization

• Works best only on large, continuous arrays

49. What type of parallelism is used in vector processors ?

 Answer: Vector processors use Data–Level Parallelism (DLP), where multiple data elements are processed in parallel using a single instruction.

50. What is an array processor ?

 Answer: An array processor is a type of parallel processor containing multiple ALUs arranged in an array, all executing the same instruction simultaneously on different data. It follows the SIMD architecture.

51. What are processing elements (PEs) ?

 Answer: Processing Elements are small, simple ALUS present in an array processor. Each PE performs the same operation on its local data under the control of a central unit.

52. What is the main advantage of array processors ?

 Answer: They provide very high performance for :

• Matrix operations

• Image processing

• Large–scale simulations.

Because many data items are processed in parallel using many PEs.

53. What is a systolic array ?

 Answer: A systolic array is a special array processor in which data flows rhythmically between PEs like a heartbeat, improving speed and reducing memory access.

54. What is the difference between vector processors and array processors ?

 Answer:

Vector Processor

1. Uses a single pipeline to process vector elements

2. Works on vector registers

3. DLP via pipelining

Array Processor

1. Uses many PEs working in parallel

2. Works on large arrays stored across PEs

3. DLP via SIMD

55. Why are array processors suitable for matrix operations ?

 Answer: Matrix multiplication requires performing the same operation on many data items, which is ideal for SIMD processing with multiple PEs.

56. What is the role of the control unit in an array processor ?

 Answer: The control unit sends the same instruction to all PEs, synchronizing their operation while each PE processes different data.