Bus Arbitration

Bus Arbitration

• The device that is allowed to initiate data transfers on the bus at any given time is called the bus master.

• In a computer system there may be more than one bus master such as processor, DMA controller etc. They share the system bus. When current master relinquishes control of the bus, another bus master can acquire the control of the bus.

• Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. The selection of bus master is usually done on the priority basis.

Approaches to bus arbitration

• In centralized bus arbitration, a single bus arbiter performs the required arbitration. The bus arbiter may be the processor or a separate controller connected to the bus.

• In distributed bus arbitration, all devices participate in the selection of the next bus master.

1. Centralized Bus Arbitration Schemes

• There are three different arbitration schemes that use the centralized bus arbitration approach. These schemes are :

a) Daisy chaining

b) Polling method

c) Independent request

Daisy chaining :

The system connections for Daisy chaining method are shown in Fig. 12.8.1.

• It is a simple and cheaper method.

• All masters make use of the same line for bus request.

• In response to a bus request the controller sends a bus grant if the bus is free. The bus grant signal serially propagates through each master until it encounters the first one that is requesting access to the bus. This master blocks the des propagation of the bus grant signal, activates the busy line and gains control of the bus. Therefore any other requesting module will not receive the grant signal and hence cannot get the bus access.

Advantages

1. It is a simple and cheaper method.

2. It requires the least number of lines and this number is independent of the number of masters in the system.

Disadvantages

1. The propagation delay of bus grant signal is proportional to the number of masters in the system. This makes arbitration time slow and hence limits the number of masters in the system.

2. The priority of the master is fixed by its physical location.

3. Failure of any one master causes the whole system to fail.

Polling method

• The system connections for polling method are shown in Fig. 12.8.2.

• In this the controller is used to generate the addresses for the masters.

• Number of address lines required depends on the number of masters connected in the system. For example, if there are 8 masters connected in the system, at least three address lines are required.

• In response to a bus request controller generates a sequence of master addresses. When the requesting master recognizes its address, it activates the busy line and begins to use the bus.

Advantages

1. The priority can be changed by altering the polling sequence stored in the controller.

2. If the one module fails entire system does not fail.

Independent request

• Fig. 12.8.3 shows the system connections for the independent request scheme.

• In this scheme each master has a separate pair of bus request and bus grant lines and each pair has a priority assigned to it.

• The built in priority decoder within the controller selects the highest priority request and asserts the corresponding bus grant signal.

Advantage

1. Due to separate pairs of bus request and bus grant signals, arbitration is fast and is independent of the number of masters in the system.

Disadvantage

1. It requires more bus request and grant signals. (2 × n signals for n modules)

2. Distributed Arbitration

• In distributed arbitration, all devices participate in the selection of the next bus master.

• Fig. 12.8.4 shows the scheme for distributed arbitration. In this scheme each device on the bus is assigned a 4–bit identification number. The number of bits used for identification number actually depends on the number of devices connected on the bus.

• When one or more devices request for the control of bus, they assert the Start–Arbitration signal and place their 4–bit ID numbers on arbitration lines,  through . These four arbitration lines are all open–collector. Therefore, more then one devices can place their 4–bit ID number to indicate that they need the control of bus.

• If one device puts 1 on the bus line and another device puts 0 on the same bus line, the bus line status will be 0. Device reads the status of all lines through inverter bus so device reads bus status 0 as logic 1.

• In this scheme the device having highest ID number has highest priority.

• When two or more devices place their ID number on bus lines then it is necessary to identify the highest ID number from the status of bus line. Consider that two devices A and B, having ID numbers 1 and 6, respectively are requesting the use of the bus. Device A puts the bit pattern 0001, and device B puts the bit pattern 0110. With this combination the status of bus–lines will be 1000; however because of inverter buffers code seen by both devices is 0111.

Each device compares the code formed on the arbitration lines to its own ID, starting from the most significant bit. If it finds a difference at any bit position, it disables its drives at that bit position and for all lower–order bits. It does so by placing a 0 at the input of these drivers. In our example, device detects a different on line  and hence it disables its drives on lines ,  and . This causes the code on the arbitration lines to change to 0110. This means that device B has won the race.

• The decentralized arbitration offers high reliability because operation of the bus is not dependent on any single device.

Review Questions

1. Define bus arbitration.

2. How does bus arbitration typically work?

3. Write note on bus arbitration

4. What is meant by bus arbitration ?

5. With a neat diagram describe the implement of distributed arbitration.

6. Explain in detail about the bus arbitration techniques in DMA.