IO Systems: Interrupt Types and Priority Handling

Interrupt Types and Priority Handling

1.  Interrupt Types

• Interrupts can be classified into different types based on their origin and handling priority :

1. Hardware interrupts

• Generated by hardware devices (I/O devices, timers, etc.).

• Example : A keyboard pressing a key or a disk signaling data transfer completion.

• Subtypes :

■ Maskable Interrupts (IRQ) : Can be turned off (masked) by the CPU if needed.

■ Non–Maskable Interrupts (NMI) : Cannot be ignored; usually used for critical errors (e.g., hardware failure).

2. Software Interrupts

• Generated by programs using special instructions.

• Often used to request operating system services (system calls).

• Example : In × 86 systems, the INT instruction triggers a software interrupt.

3. Internal Interrupts (Exceptions / Traps)

• Arise from the CPU itself due to abnormal conditions during execution.

• Examples : Divide–by–zero error, invalid opcode, page fault.

• Used for error handling and debugging.

4. External Interrupts

• Arise from external hardware devices signaling the CPU.

• Example : Mouse movement, incoming network packet.

5. Vectored and Non–Vectored Interrupts

• Vectored interrupts : The device provides the address of the ISR directly (fast handling).

• Non–Vectored Interrupts :  CPU must determine the ISR address through polling or fixed locations.

2. Priority Handling

• When interrupt requests arrive from two or more devices simultaneously, the processor has to decide which request should be serviced first and which one should be delayed. The processor takes the decision with the help of interrupt priorities. It accepts the request having the highest priority.

• In case polling to identify the interrupting device, priority is automatically assigned by the order in which devices are polled.

• No further arrangement is required to accommodate simultaneous interrupt requests.

1. Daisy–Chaining Priority

• In case of vectored interrupts, the priority of any device is usually determined by the way the device is connected to the processor. Most Common way to connect the devices is to form a daisy chain, as shown in Fig. 12.6.1.

2. Arrangement of Priority Groups

• As shown in Fig. 12.6.1, the interrupt request line () is common to all devices and the interrupt acknowledge line (INTA) is connected in a daisy–chain fashion.

• In daisy–chain fashion the signal is allowed to propagate serially through the devices.

• When more than one devices issue an interrupt request, the  line is activated and processor responds by setting the INTA line. This signal is received by device 1. Device 1 passes the signal to the device 2 only if it does not require any service. If device 1 requires service, it blocks the INTA line and puts its identification code on the data lines. Therefore, in daisy–chain arrangement, the device that is electrically closest to the processor has the highest priority.

• Fig. 12.6.2 shows another arrangement for handling priority interrupts. Here, device are organised in groups and each group is connected at a different priority level. Within a group, devices are connected in a daisy–chain.

3. Vectored Interrupts Scheme / Priority Interrupt Hardware

• Fig. 12.6.3 shows a widely used vectored interrupt scheme. As shown in Fig. 12.6.3, interrupt request signals are stored in the interrupt register. The programmable interrupt mask register is used to disable any or all of the interrupt request lines. For any AND gate, one input is the interrupt request signal from interrupt register and second input is the inverted mask condition for the same interrupt from interrupt mask register. When any interrupt is masked (1), the input to AND gate is zero, hence output goes zero. This means when interrupt is masked, the corresponding interrupt request line is disabled. When interrupt request is present for unmasked interrupt, that is fed into a priority encoder which produces the address which is then inserted into the program counter.

4. Priority Encoder

• A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.

• Table 12.6.1 shows truth table of 4–bit priority encoder.

• Table 12.6.1 shows D₃ input with highest priority and D₀ input with lowest priority. When D₃ input is high, regardless of other inputs output is (Y₁ Y₀ = 11) 11.

• The D₂ has the next priority. Thus, when D₃ = 0 and D₂ = 1, regardless of other two lower priority input, output is 10.

• The output for D₁ is generated only if higher priority inputs are 0 and so on.

• The output V (a valid output indicator) indicates, one or more of the inputs are equal to 1. If all inputs are 0, V is equal to 0 and the other two outputs (Y₁ and Y₀) of the circuit are not used.

K–map simplification

Logic diagram

Review Questions

1. List out types of interrupt. Explain any one.

2. What are priority interrupts? Explain any one interrupt priority scheme.

3. Explain daisy chain priority interrupt.