Digital Electronics

EE25301:

Digital Electronics

Course objective:

This course aims to provide a strong foundation in the principles of digital systems and logic design. It introduces number systems, Boolean algebra, and techniques for designing combinational and sequential circuits. The course also explores memory devices and programmable logic components essential for modern digital systems.

Digital Fundamentals: Number Systems – Decimal, Binary, Octal, Hexadecimal, 1‘s and 2‘s complements, Codes – Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal gates, Sum of products and product of sums, Min terms and Max terms, Karnaugh map Minimization and QuineMcCluskey method of minimization.

Combinational Logic Design: Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder, BCD Adder, Binary Multiplier, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority Encoder

Synchronous Sequential Circuits: Flip flops – SR, JK, T, D, Master/Slave. FF operation and excitation tables, Triggering of FF, Analysis and design of clocked sequential circuits – Moore/Mealy models, state minimization, state assignment, circuit implementation – Design of Counters- Ripple Counters: Binary, BCD, Modulo n, Up/Down counters-Counter for Random Sequence - Shift registers: - UniversalShiftRegister–SynchronouscountersRingcounter–Johnsoncounter.

Asynchronous Sequential Circuits: Analysis and Design of Asynchronous Sequential Circuits-Reduction of Flow Tables- Stable and Unstable states, state reduction, output specifications, cycles and races, race free assignments, Hazards: Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits

Memory and Programmable Logic Devices: ROM -PROM – EPROM – EEPROM –EAPROM, RAM –- Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using PLA, PAL,CPLD’s. TTL and CMOS Logic families

Hardware Description Language: Introduction to Verilog: Structure of Verilog module, Operators, data types, Styles of description- Data flow description, Implement logic gates, half adder and full adder using Verilog data flow description. Behavioral description: Structure, variable assignment statement, sequential statements, loop statements, Verilog behavioral description of Multiplexers (2:1,4:1,8:1) and De-multiplexers -Encoders (8 to 3), Decoders (2 to 4). latches-flipflops .

Tasks:

T1: Design logic circuits using SOP and POS forms.

T2: Compare canonical and standard forms of Boolean expressions.

T3: Design and test a BCD Adder...

T4: Demonstrate triggering methods of flip-flops..

T5: Design asynchronous sequential circuits from specifications.

Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%.

Assessment Methodology: Assignments (20%), Solution to application-oriented

problems using software(20%),review of GATE questions(20%),Internal Examinations (40%).

References:

1 Mano, M. M. (2016). Digital logic and computer design (1st ed.). Pearson India.

2 Floyd, T. L. (2025). Digital fundamentals (11th ed.). Pearson Education.

3 Roth, C. H., Jr., & Kinney, L. L. (2014). Fundamentals of logic design (7th ed.). Cengage Learning.

4 Wakerly, J. F. (2021). Digital design: Principles and practices (5th ed.). Pearson Education.

5 Leach, D. P., Malvino, A. P., & Saha, G. (2017). Digital principles and applications (7th ed.). McGraw-Hill Education.